The ATF1508AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel's proven electrically erasable Flash memory technology. With 128 logic macrocells and up to 100 inputs, it easily inte-grates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF-1508AS's enhanced routing switch matrices increase usable gate count, and increase odds of successful pin-locked design modifications.
The ATF1508AS has up to 96 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback,which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus.Each macrocell also generates a foldback logic term, which goes to a regio-nal bus. Cascade logic between macrocells in the ATF1508AS allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight suchlogic chains, each capable of creating sum term logic with a fan in of up to 40 product terms The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections:product terms and product term sel-ect multiplexer; OR/XO-R/CASCADE logic; a flip-flop; output select and enable; and logic array inputs.
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• High Density, High Performance Electrically Erasable Complex Programmable Logic Device 128 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 68, 84, 100, 160-pins 7.5 ns Maximum Pin-to-Pin Delay Registered Operation Up To 125 MHz Enhanced Routing Resources• Flexible Logic Macrocell D/T/Latch Configurable Flip Flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic utilization by burying a register within a COM output• Advanced Power Management Features Automatic 100 A Stand-By for "Z" Version (Max.) Pin-Controlled 100 A Stand-By Mode (Typical) Programmable Pin-Keeper Inputs and I/Os Reduced-Power Feature Per Macrocell• Available in Commercial and Industrial Temperature Ranges• Available in 84-pin PLCC and 100-pin PQFP and TQFP and160-pin PQFP Packages• Advanced Flash Technology 100% Tested Completely Reprogrammable 100 Program/Erase Cycles 20 Year Data Retention 2000V ESD Protection 200 mA Latch-Up Immunity • JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported• Fast In-System Programmability (ISP) via JTAG• PCI-compliant• 3.3 or 5.0V I/O pins• Security Fuse Feature
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Temperature Under Bias.......................................................................................... -40°C to +85°C
Storage Temperature ............................................................................................ -65°C to +150°C
Voltage on Any Pin with Respect to Ground ..............................................................-2.0V to +7.0V(1)
Voltage on Input Pins with Respect to Ground During Programming........................-2.0V to +14.0V(1)
Programming Voltage with Respect to Ground ........................................................-2.0V to +14.0V(1)
Post a Buying Lead
Required Field 
